1. Technical Field
This invention generally relates to integrated circuit capacitors, and more specifically relates to deep trench capacitors.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in Dynamic Random Access Memory (DRAM) markets. One particular area of concern in DRAM design is the storage capacitor used to store each memory cell. The density of DRAM designs is to a great extent limited to by the feature size of the storage capacitor.
The charge stored in the storage capacitor is subject to current leakage and for that reason the DRAM must be refreshed periodically. The time allowed between refresh without excess charge leakage is the data retention time, which is determined by the amount of charge stored at the beginning of the storage cycle and the amount of leakage current through different kinds of leakage mechanisms. For various reasons it is often preferable to minimize the leakage mechanisms so as to extend the time allowed between refresh cycles.
Several methods have been used to facilitate the shrinkage of the capacitor feature size while maintaining sufficient capacitance. For example, stacked capacitors have been located above the transfer devices. Unfortunately, this approach presents difficulties with topography and with connecting the capacitors.
Another approach has been the use of trench capacitors as storage capacitors. Trench capacitors extend the storage node into the substrate to increase the capacitance without increasing the area used on the substrate. The trench capacitor design typically uses a highly conductive single crystal silicon substrate as the counter electrode, and a highly conductive polycrystalline silicon in a deep trench as the storage electrode of the capacitor. By extending the capacitor in the vertical dimension trench capacitors allow the capacitor feature size to be decreased without decreasing the resulting capacitance
The trench capacitor was further refined by the use of a substrate plate trench design. Referring to FIG. 11, there is shown a schematic cross-sectional view of the basic buried plate trench DRAM cell. The cell includes a substrate 10 of P type semiconductor. A P well 12 is formed above an N-well 30. At the upper surface of the P well 12 a transfer device 14 is formed that includes a control gate 16 that is responsive to a word access line of the DRAM array support circuits, not shown. The transfer device 14 couples data between bit line diffused N+ region 18 and diffused N+ region 20 through the channel region formed in P well 12. A deep trench 22 is formed into the substrate 10. Surrounding the deep trench 22 is formed a buried plate 23 that serves as the capacitor counter electrode, and is connected to the buried plates of other cells through N-well 30. Inside deep trench 22 is formed the capacitor storage node comprising N+ type polysilicon electrode 24 isolated from substrate 10 by a thin dielectric layer. N+ region 20 and the polysilicon storage node 24 are connected by a buried strap 11. At the top of the storage trench 22 is a thick isolating collar 28 which serves to prevent vertical leakage. STI region 13 serves to isolate this cell from others in the array.
Unfortunately, the quest for ever decreasing device size has already begun to squeeze the traditional deep trench design. Typically, as the size of the deep trench capacitor is decreased, the effective thickness of the node dielectric must be aggressively reduced in order to maintain reasonable trench storage capacitance. Since array voltages are scaled at a slower rate than the minimum feature size, the maximum electric field seen in the capacitor dielectric has become a significant reliability concern.
Consider a trench capacitor formed with a N+ poly storage node and an N+ buried plate. In these capacitors, to help minimize the maximum electric field in the capacitor dielectric, some contemporary designs utilize a buried plate which is biased at the midpoint between the bit line low (xe2x80x9c0xe2x80x9d) and the bit line high (xe2x80x9c1xe2x80x9d) levels. This balances the capacitor voltage swing and thus minimizes the maximum electric field seen in the dielectric and minimizes leakage through the dielectric. For example, where the capacitor storage node swings between 1.5 volts for a high level, and 0 volts for a low level, the buried plate would be biased at 0.75 volts. This balancing technique reduces the maximum voltage across the node dielectric to one-half of the bit line swing. In the above example, the maximum voltage across the capacitor (from storage node to buried plate) is limited to xc2x10.75 volts, where a unbiased plate would have resulted in a maximum voltage of 1.5 volts. Unfortunately, this technique adds significant complexity to the design in that a charge pump and voltage distribution system is required to effectively bias the buried plate. This technique also has the disadvantage of increasing power consumption due to increased leakage current from the biased buried plate to the substrate. This technique also has the disadvantage of coupling noise from the bias circuitry to the capacitor.
Thus, there are needed improved memory capacitor designs that minimize the amount of voltage across the dielectric while maintaining device simplicity and minimizing power consumption.
The preferred embodiment of the present invention provides an improved capacitor design that overcomes many of the limitations of the prior art. In particular, the preferred embodiment uses germanium in the storage node to intrinsically balance the electric fields seen in the capacitor dielectric, thus minimizing the maximum electric field. The difference in electric potential seen across the capacitor is the difference between the storage node conduction band potential and the counter electrode conduction band potential. The preferred embodiment of the present invention uses germanium to adjust the work function of the storage node. Specifically, the addition of germanium modifies the fermi level of the storage node, moving the fermi level towards the vacuum level. This modification of the fermi level reduces the difference in conduction band potentials between the storage node and the counter electrode, thus reducing the maximum electric potential seen across the capacitor.
In the preferred embodiment, p-type doped silicon germanium is formed in the trench capacitor adjacent to the capacitor dielectric layer. A barrier layer is then formed over the doped silicon germanium, and the remaining storage node area is filled with n+-type polysilicon. The p-type doped silicon germanium adjusts the workfunction of the capacitor storage node, moving the fermi level toward the vacuum level. This minimizes the maximum difference between conduction potentials of the storage node and the buried plate, which serves as the counter electrode. This has the effect of intrinsically balancing the electric potential seen across the dielectric for stored high and stored low situations, and thus reduces the maximum electric potential seen across the capacitor dielectric. This solution improves the reliability of the capacitor, especially those capacitors with relatively thin dielectric layers, without requiring additional circuitry to bias the buried plate, and without increasing power consumption. The preferred embodiment also reduces leakage current through the capacitor dielectric, thus increasing signal retention time.
The foregoing and other features and advantages of the present invention will be apparent from the following more particular description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.